A conventional clock/data recovery (CDR) uses a reference clock in order to bring the voltage controlled oscillator (VCO) output frequency into the vicinity of the data rate before phase acquisition. In certain applications, such as power and/or area limited circuits, a reference clock may not be present or may be difficult to route to the CDR. Accordingly, reference-less CDRs may be used in such situations.
However, in frequency detector (FD) of reference-less CDRs, the latency of frequency down control signals is much larger than the latency of frequency up control signals due to asymmetrical architecture within the frequency detector. Thus, when the input data rate is much lower than the VCO frequency, the frequency detector cannot reduce the VCO's frequency low enough to match the input data rate. Thus, the frequency cannot lock to the data rate and the data may be lost.